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The Serial Peripheral Interface Bus or SPI (often pronounced "spy") bus is a synchronous serial data link standard designed by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines.

Contents 1 Interface 2 Operation 2.1 Transmission 2.2 Clock polarity and phase 2.2.1 Modes 2.3 Daisy chain SPI configuration 2.4 Valid SPI communications 3 Pros and cons of SPI 3.1 Advantages 3.2 Disadvantages 4 Applications 5 Standards 6 Similar protocols 6.1 Queued Serial Peripheral Interface (QSPI) 7 References 8 See also 9 External links

The SPI bus specifies four logic signals.

• SCLK — Serial Clock (output from master)
• MOSI/SIMO — Master Output, Slave Input (output from master)
• MISO/SOMI — Master Input, Slave Output (output from slave)
• SS — Slave Select (active low; output from master)

Sometimes, the following naming convention is used:

• SCLK — Serial Clock (output from master)
• SDI — Serial Data In
• SDO — Serial Data Out
• CS — Chip Select (active low; output from master)

The latter convention requires that SDO on the master be connected to SDI on the slave, and vice-versa.

SPI port pin names for particular IC products may differ from those depicted in this illustration.

The SPI bus can operate with a single master device and with one or more slave devices.

If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some slaves require the falling edge (high->low transition) of the slave select to initiate an action such as the MAX1242 by Maxim IC, an ADC, that starts conversion on said transition. With multiple slave devices, an independent SS signal is required from the master for each slave device.

Most devices have tri-state outputs that become high impedance ("disconnected") when the device is not selected.

To begin a communication, the master pulls the slave select low for the desired chip. If a waiting period is required (such as for analog-to-digital conversion) then the master must wait for at least that period of time. The master then generates a clock frequency less than or equal to the maximum frequency the slave device supports (this is usually configured in the master on a per-transmission basis). During clock generation, a full duplex transmission occurs:

• the master sends data on the MOSI line; the slave reads from the MOSI line
• the slave sends data on the MISO line; the master reads from the MISO line

Not all transmissions require all four of these operations to be meaningful but they do happen. Generally, a transmission happens in single byte increments and a master can initiate multiple 8-bit transmissions if it wishes/needs.

Every other slave on the bus that doesn't have their slave select line pulled low must disregard the clock, MOSI, and MISO lines.

In addition to setting the clock frequency, the master can optionally set the clock polarity and clock phase with respect to the data. The SPI Block Guide ^[1] names these two options as CPOL and CPHA respectively.

The timing diagram is shown to the right and described below:

• At CPOL=0 the base value of the clock is zero
  • For CPHA=0, data is read on the clock's rising edge (low->high transition) and data is changed on a falling edge (high->low clock transition).
  • For CPHA=1, data is read on the clock's falling edge and data is changed on a rising edge.
• At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
  • For CPHA=0, data is read on clock's falling edge and data is changed on a rising edge.
  • For CPHA=1, data is read on clock's rising edge and data is changed on a falling edge.

This adds more flexibility to the communication channel between the master and slave.

The combinations of polarity and phases are often referred to as modes which are commonly numbered according to the following convention:

Mode	CPOL	CPHA
0	0	0
1	0	1
2	1	0
3	1	1

Some products with SPI bus are designed to be capable of being connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of what it received during the first group of clock pulses. The whole chain acts as an SPI communication shift register. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave.

SPI communications are normally 8 bits long or an integer multiple thereof. Some slave devices are designed to ignore any invalid SPI communications in which the number of clock pulses is not an integer multiple of 8. Even so, in other contexts, it is perfectly valid to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain of a digital IC.

• Full duplex communication for higher throughput
• Higher throughput than I²C
• No addressing means reduced overhead which can be advantageous in small number (if not single) slaves

• Requires more pins on IC packages:
  • Half duplex would require one fewer pin (possible in newer controllers with bidirectional mode; important slaves like EEPROMs tristate their outputs when receiving data from the master and don't care about the input when sending data back)
  • No addressing requires chip selects
• No hardware flow control
• No slave acknowledgment (the master could literally be "talking" to nothing and not know it)
• Is not a multi-master bus

The SPI full-duplex capability make it very simple and efficient for single master/single slave applications. The complexity of the interface grows as the number of slave devices increases due to its lack of built-in addressing. Some devices use the full-duplex mode to implement an efficient, high-speed data stream for applications such as digital audio, digital signal processing, or telecommunications channels.

In practice, many devices have exceptions. Some read data as SCLK goes high, and others read data as SCLK goes low. Sending data from slave to master is almost always during the opposite clock level as master to slave. Some devices have two clocks, one to "capture" or "display" data, and another to clock it into the device. Many of these "capture clocks" can be run from the SS line.

The SPI bus is a sort of de facto standard, rather than one agreed by any international committee. The reason for this is probably its essential simplicity.

The queued serial peripheral interface (QSPI) also uses a synchronous serial bus to communicate with external peripherals and other MCUs. It is compatible with the serial peripheral interface (SPI). It differs by having a data queue with programmable queue pointers that allow some data transfers without CPU intervention^[2]. It also has a wrap-around mode that allows continuous transfers to and from the queue with no CPU intervention. As a result, the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/delay.

1. ^ SPI Block Guide V03.06, Freescale Semiconductor
2. ^ Queued Serial Module Reference Manual, Freescale Semiconductor

• I²C
• 1-Wire
• Microwire
• Computer bus
• Controller Area Network
• Serial communications
• Peripheral
• Interface

• Introduction to Serial Peripheral Interface article on embedded.com
• Serial buses information page
• SPI Introduction with helpful diagrams